The ongoing focus on miniaturization and the increasing complexity and speed requirements of integrated circuits demand for a continuous higher density integration. To achieve this, there is an ongoing downscaling of the dimensions of the active devices as well as of the structures interconnecting these devices. These interconnect structures can comprise multiple metal levels which are, dependent on the aimed interconnect pattern, either separated one from another by means of interlevel insulating layers or connected one to the other by means of a conductive connection through the insulating layer. Intra-level insulating layers are used to provide isolation within a metal level. Besides this downscaling of the dimensions, additional measures are required to be able to meet the stringent speed specifications like e.g. the signal delay. Conventionally the metal levels are Aluminum layers while the insulating layers are oxide layers. In order to reduce the signal delay one can choose a metal layer with a higher conductivity compared to Aluminum, e.g. a Cu-containing metal layer, and/or choose insulating layers with a lower dielectric constant compared to oxide layers.
This demand for insulating layers with a low dielectric constant has lead to an intensified search for new low K materials to be used as insulating layers. A low ε material, a low K material and a material with a low permittivity are all alternative expressions for a material with a low dielectric constant, at least for the purposes of this disclosure. The most desirable material should have a low K value, low mechanical stress, high thermal stability and low moisture absorption. Furthermore, the desired material should be selected based on the compatibility with state-of-the-art semiconductor processing steps and tools. Among these new materials are the organic spin-on materials, having a K value in the range from 2.5 to 3, the porous polymers, and the inorganic low-K materials as e.g. xerogels having a K value typically lower than 1.5. The organic materials are of particular interest because they feature simplified processing, excellent gap-fill and planarization.
Nowadays, there are two major ways of fabricating interconnect structures. In the conventional way as a start a conductive layer, e.g. a metal layer, is formed on an insulating layer (or on the substrate) and patterned thereafter usually by means of reactive ion etching (RIE). Another way is the damascene technology. In the damascene technology, first an insulating layer is deposited and patterned and thereafter a metal layer is deposited to fill the openings, eventually followed by a planarization step to remove the metal excess. The damascene technology has the additional advantage that the difficult metal RIE step is avoided. Damascene processing reduces the problem to dry etching of an insulating layer or a stack of insulating layers. This technique allows the build up of horizontal metal patterns as well as vertical metal connections in the surrounding insulating layers. These vertical metal connections are required in order to be able to provide a conductive connection between two horizontal metal patterns being processed in different metal levels. To provide such a connection, usually first openings have to be formed in the insulating layer or in the stack of insulating layers between two different metal levels and filled thereafter with a conductive material. Examples of such openings are via holes or contact holes or trenches. To meet the high density integration requirements, the diameter of these openings is continuously decreasing, while at the same time the aspect ratio of these openings is increasing. Due to the small diameter and the high aspect ratios, the creation of these openings, especially the lithographic steps and the etching steps involved, is a critical process. Therefore, etching of polymers used as insulating layers requires highly anisotropic etching capabilities.
U.S. Pat. No. 5,269,879 is related to the etching of silicon oxide, silicon nitride or oxynitride layers in order to create a via hole extending through such a layer to an underlying electrically conductive layer. Particularly plasma etching is disclosed in an ambient including a fluorine-containing gas, a small amount of a passivating gas, i.e. nitrogen, and eventually an inert gas. This passivating gas is added to the plasma to prevent the sputtering of the underlying electrically conductive layer.
U.S. Pat. No. 5,176,790 is related to the etching of mainly silicon oxide, silicon nitride or oxynitride layers in order to create a via hole extending through such a layer to an underlying electrically conductive layer. Particularly plasma etching is disclosed in an ambient including a fluorine-containing gas, a nitrogen-containing gas, and eventually an inert gas. This nitrogen-containing gas is added to the plasma to prevent the sputtering of the underlying electrically conductive layer. However the amount of nitrogen-containing gas in the ambient is limited. This amount ranges from 1 volume part of nitrogen-containing gas per 2 volume parts of fluorine-containing gas to 1 volume part of nitrogen-containing gas per 15 volume parts of fluorine-containing gas.